As image sensors mounted on digital still cameras, digital video cameras, mobile phone cameras, and endoscope cameras, solid state imaging apparatus called CCD sensors or CMOS sensors which include a substrate, e.g., a silicon chip, and an array of pixels containing a photodiode and read out signal charge corresponding to photoelectrons generated in the photodiode of each pixel by a CCD or CMOS readout circuit are known.
The known solid state imaging apparatus includes not only the photodiode but a signal readout circuit and an accompanying multilevel interconnect formed on the semiconductor substrate for every pixel. Therefore, as the pixel pitch reduces, the area ratio of the circuit region in unit pixel becomes larger, which of necessity raises the problem of reduction in the effective area of the photodiode, i.e., reduction of a pixel aperture ratio. Reduction of aperture ratio leads to reduction of sensitivity.
To overcome the problem, a stacked or tandem solid state imaging apparatus has been proposed as in JP 1-34509B, in which a photoelectric layer is superposed on a semiconductor substrate having formed therein circuitry and wiring to increase the pixel aperture ratio. A representative structure of such a configuration includes a semiconductor substrate and a large number of photoelectric devices arrayed two-dimensionally in parallel to the substrate, the photoelectric devices each including a pixel electrode formed on the substrate, a photoelectric layer stacked on the pixel electrode, and a counter electrode stacked on the photoelectric layer. With a bias voltage applied between the pixel electrode and the counter electrode, excitons photogenerated in the photoelectric layer are dissociated into electrons and holes. The electrons or holes are swept toward the pixel electrode by the bias voltage, and the signals corresponding to the electrons or holes collected at the pixel electrode are read out by a CCD or CMOS readout circuit formed in the semiconductor substrate.
Photoelectric devices having a photoelectric layer made of an organic semiconductor are known from, e.g., U.S. Pat. No. 6,300,612, JP 2007-88033A and JP 2008-72090A. Because a photoelectric layer of an organic semiconductor has a large absorption coefficient, it is effective with a reduced film thickness, involves little charge diffusion to adjacent pixels, and thereby provides a photoelectric device with minimized optical and electrical cross-talk.
JP 2007-88033A discloses a photoelectric device having a photoelectric layer of an organic semiconductor between opposing electrodes. Provided between one of the electrodes and the photoelectric layer is a charge blocking layer for blocking charge injection from that electrode to the photoelectric layer. The ionizing potential and electron affinity of the charge blocking layer are specified in relation to the ionization potential of the adjacent electrode and the electron affinity of the organic photoelectric layer.
JP 2008-72090A discloses a photoelectric device having a photoelectric layer of an organic semiconductor between opposing electrodes. Provided between at least one of the electrodes and the photoelectric layer is a multi-layered charge blocking layer.